The present invention relates to fabrication process monitoring techniques, and more particularly, to a method and system of semiconductor fabrication fault analysis.
A conventional semiconductor factory typically includes the requisite fabrication tools to process semiconductor wafers for a particular purpose, such as photolithography, chemical-mechanical polishing, or chemical vapor deposition. During manufacturing, the semiconductor wafer passes through a series of process steps, performed by various fabrication tools. For example, in the production of an integrated semiconductor product, the semiconductor wafer passes through up to 600 process steps. The costs for automated production are influenced to a great extent by how well and efficiently the manufacturing process can be monitored or controlled, so that the ratio of defect-free products to the overall number of products manufactured (i.e., yield ratio) achieves as great a value as possible. Unfortunately, the individual process steps are subject to fluctuations and irregularities, which in the worst case may mean, for example, the defect of a number of chips or the entire wafer. Therefore, each individual process step must be carried out as stably as possible in order to ensure an acceptable yield after processing of a wafer is completed.
Integrated circuits are typically fabricated by processing one or more wafers as a “lot” with a series of wafer fabrication tools (i.e., “processing tools”). During integrated circuit fabrication, various test structures are fabricated on a wafer to extract information on the process and device performance for fault analysis. Wafer acceptance test (WAT) data is generated by electrical measurements of these test structures after completing the entire fabrication process. Several sites located on the fixed locations on each wafer are selected, from which over 100 WAT parameters are measured. Statistical analysis and process diagnosis based on end-of-line WAT data provide an assessment of overall process performance and its impact on product yield. In order to ensure acceptable yield, the historical WAT data is often examined to discover critical fabrication issues that cause serious defects or errors.
Since WAT measurements reflect the overall results of the entire fabrication process, their statistical characteristics are usually complicated. Conventionally, several statistical methods, such as Analysis of Variance (ANOVA), Nonparameteric Statistics, box plots or trend charts, have been employed for fault analysis of WAT data. A box plot is used to determine if any of the individual tools, recipes or operations, lie outside an acceptable range of variation. A trend chart is useful for WAT data comparison and drift analysis of fabrication tools. ANOVA and Nonparameteric Statistical methods are employed to detect commonality factors (e.g., tools, recipes or operations) and the impact thereof on faulty wafer lots. Although the described methods are feasible, several problems remain. Box plots and trend charts are incapable of detecting common factors because the calculation thereof is limited to a single fabrication tool, recipe or operation. The ANOVA and Nonparameteric Statistics often discover incorrect common factors because the size of WAT sample data is often lower than their requirement (ANOVA and Nonparameteric Statistics require at least 30 and 5 samples respectively). Additionally, conventional methods of fabrication fault analysis separately calculate each WAT parameter without considering such important factors as the common features among WAT parameters, thereby generating erroneous results for critical fabrication issues.
In view of these limitations, a need exists for a system and method for semiconductor manufacturing fault analysis with the increased accuracy.